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參數(shù)資料
| 型號： | 935267636118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP1-48 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 86K |
| 代理商： | 935267636118 |
Philips Semiconductors
Product specification
SSTL16877
14-bit SSTL_2 registered driver with
differential clock inputs
2
2000 Aug 15
853-2198 23523
FEATURES
Stub-series terminated logic for 2.5 V VDDQ (SSTL_2)
Optimized for DDR (Double Data Rate) SDRAM applications
Supports SSTL_2 signal inputs and outputs
Flow-through architecture optimizes PCB layout
Meets SSTL_2 class I and class II specifications
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2500 V per MIL STD 833 Method 3015
and 200 V per Machine Model
Full DDR1 PC333 solution @ 2.5 V when used with PCKV857
Mixed 2.5 V (PC266) / 3.3 V (PC333) solution when used with
PCK857
Same form, fit, and function as SSTV16857
DESCRIPTION
The SSTL16877 is a 14-bit SSTL_2 registered driver with differential
clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ
must not exceed VCC. Inputs are SSTL_2 type with VREF normally at
0.5*VDDQ. The outputs support class I which can be used for
standard stub-series applications or capacitive loads. Master reset
(RESET) asynchronously resets all registers to zero.
The SSTL16877 is intended to be incorporated into standard DIMM
(Dual In-Line Memory Module) designs defined by JEDEC, such as
DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.
Different from traditional SDRAM, DDR SDRAM transfers data on
both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of
333 MHz. The modules require between 23 and 27 registered
control and address lines, so two 14-bit wide devices will be used on
each module. The SSTL16877 is intended to be used for SSTL_2
input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VDDQ
Q5
Q6
Q9
Q10
D12
D11
D10
D9
D8
RESET
VREF
GND
VCC
CLK+
CLK–
D7
D6
D5
D4
D3
VCC
GND
D2
D1
21
22
23
24
25
26
27
28
VDDQ
Q14
D14
D13
GND
VCC
Q1
Q2
GND
Q3
Q4
GND
VDDQ
Q7
VDDQ
GND
Q8
VDDQ
GND
Q11
Q12
GND
Q13
SW00311
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay; CLK to Qn
CL = 30 pF; VDDQ = 2.5 V
2.4
ns
CI
Input capacitance
VCC = 2.5 V
2.9
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD
VCC2 x fi ) (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V;
(CL
VCC2
fo) = sum of the outputs.
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