參數(shù)資料
型號(hào)： 935267925557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 39/76頁(yè)
文件大?。?/td> 567K
代理商： 935267925557
Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
44
6.13
32kHz PLL Oscillator with Seconds Timer
6.13.1
XTAL3,4 Oscillator Circuitry
The input signal SELXTAL1 connected to logic “0” selects the 32kHz
oscillator together with the PLL instead of the XTAL1,2 oscillator,
which is halted. XTAL2 is floating in that case.
The 32kHz oscillator consists of an inverter, which forms a Pierce
oscillator with the on-chip components C1,C2,Rf and an external
crystal of 32768 Hz.
During the following situations, the inverter is switched to tristate and
XTAL3 is pulled to Vss :
during Power-down Mode, when the PLL control register bit
RUN32 (PLLCON.7) was set to ’0’;
during Reset (RSTIN = HIGH) ;
when the XTAL1,2 oscillator is selected (SELXTAL1 = HIGH).
6.13.2
PLL CCO
A current controlled oscillator (CCO) generates a clock frequency
fCCO of approx. 32 , 38 , 44 or 50 MHz , controlled by the PLL, with
the 32kHz oscillator as the reference clock. The system clock
frequency fCLK can be varied under software control by changing the
contents of the PLL control register (PLLCON):
fCCO can be changed via the PLLCON bits FSEL(1:0) (see
Table 41). The maximum locking time is 10 ms1.
During the stabilization phase, no time critical routines should be
executed.
The system clock frequency fCLK is derived from fCCO under control
of the PLLCON bits FSEL(4:0) (see Table 41).
If only FSEL(4:2) is changed but not FSEL(1:0), then it takes about
1us until the new frequency is available.
Changing the system clock frequency has to be done in two steps.
From HIGH to LOW frequencies:
First change (FSEL(4:2), then FSEL (1:0).
From LOW to HIGH frequencies:
First change only FSEL (1:0) and after a stabilization phase of
10 ms change FSEL (4:2).
6.13.3
PLL Control Register – PLLCON
PLLCON is a special function register, which can be read and
written by software. It contains the control bits:
to select one of several system clock frequencies (see Table 41);
the seconds interrupt flag: SECINT
to enable the seconds interrupt flag: ENSECI
the RUN32 bit, which defines if during Power-down Mode the
32kHz oscillator is halted or stays running.
PLLCON is initialized to 0DH upon Reset (RSTIN = ‘1’) or Watchdog
Timer Overflow. PLLCON = 0DH corresponds to a system clock
frequency of 11.01 MHz.
Figure 44. PLL control register (PLLCON).
7
6
54
321
0
PLLCON (F9H)
RUN32
ENSECI
SECINT
FSEL.4
FSEL.3
FSEL.2
FSEL.1
FSEL.0
Table 41.
PLLCON
SYMBOL
BIT
FUNCTION
RUN32
PLLCON.7
RUN32 = 0: The 32 kHz oscillator halts during Power-down.
RUN32 = 1: The 32 kHz oscillator stays running during Power-down.
ENSECI
PLLCON.6
Enable the seconds interrupt. (enabling INT1 is also required)
SECINT
PLLCON.5
Seconds interrupt requested by an overflow of the seconds timer (which occurs every second) or via writing
a ‘1’ to this bit. SECINT can only be cleared by writing a ’0’ to this bit .
FSEL.4
PLLCON.4
System clock frequency in MHz
to
FSEL.0
to
PLLCON.0
11
FSEL[1:0]
10
01
00
15.73
7.86
9.44
11.01
12.58
3.93
4.72
5.51
6.29
010
011
100
FSEL[4:2]
Other combinations, than mentioned above, are reserved and may not be selected. This allows to generate the standard baudrates 19200,
9600, 4800, 2400 and 1200 Baud, when using the UART and Timer1.
NOTE:
1. This parameter is characterized.
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