參數(shù)資料
型號(hào)： 935268471118
廠商： NXP SEMICONDUCTORS
元件分類： 編、解碼器及復(fù)用、解復(fù)用
英文描述： 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO14
封裝： 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14
文件頁(yè)數(shù)： 7/14頁(yè)
文件大小： 116K
代理商： 935268471118
Philips Semiconductors
Product data
PCA9542
2-channel I2C multiplexer and interrupt logic
2
2002 Mar 28
853–2177 27939
FEATURES
1-of-2 bi-directional translating multiplexer
I2C interface logic; compatible with SMBus
2 Active Low Interrupt Inputs
Active Low Interrupt Output
3 address pins allowing up to 8 devices on the I2C bus
Channel selection via I2C bus
Power up with all multiplexer channels deselected
Low Rds
ON switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
No glitch on power-up
Supports hot insertion
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant Inputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000V per JESD22-C101
Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Package Offer: SO14, TSSOP14
DESCRIPTION
The PCA9542 is a 1-of-2 bi-directional translating multiplexer,
controlled via the I2C bus. The SCL/SDA upstream pair fans out to
two SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register. Two interrupt inputs, INT0 and INT1,
one for each of the SCx/SDx downstream pairs, are provided. One
interrupt output, INT, which acts as an AND of the two interrupt
inputs, is provided.
A power-on reset function puts the registers in their default state and
initializes the I2C state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9542. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts
can communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
1
2
3
4
5
6
78
9
10
11
12
13
14
A0
A1
A2
INT0
SD0
SC0
VSS
VDD
SDA
SCL
SD1
SC1
INT1
INT
SW00475
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
A0
Address input 0
2
A1
Address input 1
3
A2
Address input 2
4
INT0
Active LOW interrupt input 0
5
SD0
Serial data 0
6
SC0
Serial clock 0
7
VSS
Supply ground
8
INT1
Active LOW interrupt input 1
9
SD1
Serial data 1
10
SC1
Serial clock 1
11
INT
Active LOW interrupt output
12
SCL
Serial clock line
13
SDA
Serial data line
14
VDD
Supply voltage
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
14-Pin Plastic SO
–40 to +85
°C
PCA9542D
SOT108-1
14-Pin Plastic TSSOP
–40 to +85
°C
PCA9542PW
SOT402-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
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