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參數(shù)資料
| 型號(hào)： | 935270276118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | HEX 1-INPUT INVERT GATE, PDSO14 |
| 封裝： | SOT-402, 14 PIN |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 85K |
| 代理商： | 935270276118 |
January 1995
4
Philips Semiconductors
Product specication
Hex inverting Schmitt trigger
HEF40106B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In → On
5
90
180
ns
63 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
35
70
ns
24 ns
+ (0,23 ns/pF)
15
30
60
ns
22 ns
+ (0,16 ns/pF) CL
5
75
150
ns
48 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
35
70
ns
24 ns
+ (0,23 ns/pF) CL
15
30
60
ns
22 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
5
60
120
ns
10 ns
+ (1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60
ns
9 ns
+ (0,42 ns/pF) CL
15
20
40
ns
6 ns
+ (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (
W)
Dynamic power
5
2 300 fi +∑ (foCL) × VDD2
where
dissipation per
10
9 000 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
20 000 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
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