參數(shù)資料
型號(hào)： 935270674112
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封裝： 3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16
文件頁(yè)數(shù)： 19/20頁(yè)
文件大小： 153K
代理商： 935270674112
Philips Semiconductors
Product data
PCA9557
8-bit I2C and SMBus I/0 port with reset
2002 Dec 13
8
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 9).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 9. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 10).
System configuration
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 11).
SDA
SCL
SW00365
S
P
SDA
SCL
START condition
STOP condition
Figure 10. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I2C
MULTIPLEXER
SLAVE
Figure 11. System configuration
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