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參數(shù)資料
| 型號： | 935272028125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | LVC/LCX/Z SERIES, 1-INPUT INVERT GATE, PDSO5 |
| 封裝： | PLASTIC, SOT-753, SC-74A, 5 PIN |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 137K |
| 代理商： | 935272028125 |
2003 Mar 03
2
Philips Semiconductors
Product specication
Inverter with open-drain output
74LVC1G06
FEATURES
Wide supply voltage range from 1.65 to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V)
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +125 °C.
DESCRIPTION
The 74LVC1G06 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Input can be driven from either 3.3 or 5 V devices. These
features allow the use of these devices in a mixed
3.3 and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant
for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging backflow current through the
device when it is powered down.
The 74LVC1G06 provides the inverting buffer.
The output of the device is an open drain and can be
connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND
functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay inputs A to output Y
VCC = 1.8 V; CL = 30 pF; RL =1k
3ns
VCC = 2.5 V; CL = 30 pF; RL = 500
1.9
ns
VCC = 2.7 V; CL = 50 pF; RL = 500
2.5
ns
VCC = 3.3 V; CL = 50 pF; RL = 500
2.3
ns
VCC = 5.0 V; CL = 50 pF; RL = 500
1.7
ns
CI
input capacitance
5
pF
CPD
power dissipation capacitance per buffer
VCC = 3.3 V; notes 1 and 2
6
pF
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