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參數(shù)資料
| 型號： | 935272239118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | AVC SERIES, 20 1-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 4.40 MM, 0.40 MM PITCH, PLASTIC, MO-194, SOT-481-2, TSSOP-56 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 113K |
| 代理商： | 935272239118 |
Philips Semiconductors
Product data
74AVC16836A
20-bit registered driver with inverted register enable
and Dynamic Controlled Outputs
(3-State)
2002 Aug 02
6
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3 ± 0.3 V
VCC = 2.5 ± 0.2 V
VCC = 1.8 ± 0.15 V
VCC =
1.5
± 0.1 V
VCC =
1.2 V
UNIT
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
TYP1
MAX
MIN
MAX
TYP
Propagation
delay
An to Yn
1, 7
0.7
1.5
2.7
0.8
1.7
3.2
1.0
2.4
4.4
2.0
5.3
4.7
ns
tPHL/tPLH
Propagation
delay
LE to Yn
2, 7
0.7
1.7
3.4
1.0
2.1
3.5
1.5
2.7
5.0
2.0
5.6
5.0
ns
Propagation
delay
CP to Yn
3, 7
0.7
1.6
3.0
0.8
1.7
3.2
1.2
2.3
4.1
2.0
4.7
5.7
ns
tPZH/tPZL
3-State output
enable time
OE to Yn
6, 7
1.0
1.9
3.6
1.0
2.4
4.0
1.5
3.0
5.4
2.5
6.8
6.0
ns
tPHZ/tPLZ
3-State output
disable time
OE to Yn
6, 7
1.0
2.5
4.8
1.0
2.1
4.7
1.5
3.7
7.5
2.5
7.6
6.6
ns
t
CP pulse width
HIGH or LOW
3, 7
1.0
–
1.2
–
2.0
–
ns
tW
LE pulse width
HIGH
2, 7
1.0
–
1.2
–
2.0
–
ns
tS
Set-up time
An to CP
5, 7
0.2
0
–
0.3
0
–
0.2
0
–
0.3
–
0
ns
tSU
Set-up time
An to LE
4, 7
0.3
0
–
0.6
0.2
–
0.9
0.4
–
1.3
–
1.2
ns
t
Hold time
An to CP
5, 7
1.2
0.5
–
0.6
0.2
–
0.6
0.2
–
0.6
–
0.1
ns
th
Hold time
An to LE
4, 7
1.0
0.5
–
0.5
0.1
–
0.4
0
–
0.2
–
–0.7
ns
fmax
Maximum clock
pulse frequency
3, 7
500
–
400
–
250
–
MHz
NOTE:
1. All typical values are measured at Tamb = 25°C and at VCC = 1.8 V, 2.5 V, 3.3 V.
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