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參數(shù)資料
| 型號(hào)： | 93716YF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93716 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | LEAD FREE, MO-150, SSOP-28 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 93716YF-T |
Integrated
Circuit
Systems, Inc.
ICS93716
0420H—09/10/08
Block Diagram
Low Cost DDR Phase Lock Loop Clock Driver
Pin Configuration
28-Pin SSOP and TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
I
2C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Bypass mode on B revision only
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <75ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 550ps - 950ps
Functionality
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
P
D
V
AT
N
I
_
K
L
CC
N
I
_
K
L
CT
K
L
CC
K
L
CT
T
U
O
_
B
FC
T
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O
_
B
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V
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H
L
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5
.
2
)
m
o
n
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z
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0
2
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Z
f
o
D
N
GL
H
L
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L
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f
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d
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s
a
p
y
B
D
N
GH
L
H
L
H
L
f
o
/
d
e
s
a
p
y
B
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
PLL
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
CLKT2
CLKC2
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
FBINC
FBINT
FB_OUTT
FB_OUTC
CLKT3
CLKC3
GND
ICS93716
1
2
3
4
5
6
7
8
9
10
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12
13
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28
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15
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