參數(shù)資料
型號: 93725AF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 93725 SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 0.300 INCH, MO-118, SSOP-48
文件頁數(shù): 1/8頁
文件大?。?/td> 94K
代理商: 93725AF
Integrated
Circuit
Systems, Inc.
ICS93725
0606A—08/01/03
Block Diagram
DDR and SDRAM Zero Delay Buffer
Pin Configuration
48-Pin SSOP
Recommended Application:
DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/
650 & 735/740/746 style chipsets.
Product Description/Features:
Low skew, Zero Delay Buffer
1 to 13 SDRAM PC133 clock distribution
1 to 6 pairs of DDR clock distribution
I
2C for functional and output control
Separate feedback path for both memory mode to
adjust synchronization.
Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs
Frequency support for up to 200MHz (DDR 400)
Individual I
2C clock stop for power mananagement
CMOS level control signal input
Switching Characteristics:
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 550ps -
1150ps
DUTY CYCLE: 47% - 53%
*Internal Pull-up Resistor of 120K to VDD
Functionality
E
D
O
M8
4
N
I
P
D
V
5
.
2
_
3
.
3
R
D
e
d
o
M
1
=
R
D
_
L
E
SV
5
.
2
D
S
/
R
D
e
d
o
M
0
=
R
D
_
L
E
SV
3
.
3
VDD3.3
SDRAM0
SDRAM1
SDRAM2
SDRAM3
GND
VDD3.3
SDRAM4
SDRAM5
BUFFER_IN
SDRAM6
SDRAM7
GND
VDD3.3
SDRAM8
SDRAM9
SDRAM10
SDRAM11
GND
VDD3.3
SDRAM12
SDFB_OUT
SDFB_IN
GND
SEL_DDR*
DDRFB_IN
DDRFB_OUT
VDD2.5
DDRT5
DDRC5
DDRT4
DDRC4
GND
VDD2.5
DDRT3
DDRC3
DDRT2
DDRC2
GND
VDD2.5
DDRT1
DDRC1
DDRT0
DDRC0
GND
VDD2.5
SCLK
SDATA
ICS93725
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR*
PLL1
SDRAM (12:0)
DDRFB_OUT
SDRAMFB_OUT
BUFFER_IN
SDRAMFB_IN
DDRFB_IN
SDATA
SCLK
Control
Logic
Config.
Reg.
3
DDRT (5:0)
DDRCC (5:0)
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