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參數(shù)資料
| 型號： | 93732AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, GREEN, MO-150, SSOP-28 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 126K |
| 代理商： | 93732AFLFT |
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Home > Products > Timing Solutions > PC-Notebook-Server Clocks > DDR I and DDR II Buffers > Zero Delay Buffers > 93732
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93732 (Zero Delay Buffers)
Description
DDR Zero Delay Clock Buffer
Market Group
PC CLOCK
Additional Info
Low skew, low jitter PLL clock driver Max frequency supported = 266MHz (DDR 533) I2C for functional and output control Feedback pins for
input to output synchronization Spread Spectrum tolerant inputs 3.3V tolerant CLK_INT input
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Related Orderable Parts
Attributes
93732AF
93732AFLF
93732AFLFT
93732AFT
93732AG
93732AGT
Voltage
3.3 V (PY28)
3.3 V (PYG28)
3.3 V (PY28)
3.3 V (PG28)
Package
SSOP 28
TSSOP 28
Speed
NA
Temperature
C
Status
Active
Sample
Yes
No
Yes
No
Minimum Order
Quantity
141
1000
96
1000
Factory Order
Increment
47
1000
48
1000
Related Documents
Type
Title
Size
Revision Date
Datasheet
93732 Datasheet
95 KB
03/24/2006
Page 1 of 2
08-Jun-2007
mhtml:file://C:\93732.mht
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 93732AF | 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| 93732YFLFT | 93732 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| 93735AF-T | 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 93735AFLF | 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 93735AF | 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 937333-000 | 制造商:ELO Touch Solutions 功能描述:20.4IN FLAT ANTIGLARE;SAMPLE!! |
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| 937-345 | 功能描述:支架與墊片 Nylon Tubular,0.345 in. Length,0.125 OD,0.09 ID,White RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc |
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