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參數(shù)資料
| 型號(hào)： | 93735AF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93735 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 0.300 INCH, MO-118, SSOP-48 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 155K |
| 代理商： | 93735AF-T |
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer
ICS93735
REV F 02/11/07
ICS93735
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Operating Condition
Timing Requirements
Switching Characteristics
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog / Core Supply Volta
AVDD
2.3
2.5
2.7
V
Input Voltage Level
VIN
22.5
3
V
Output Differential Pair
Crossing Voltage
1.32
V
VOC
66/100/133/166MHz, VDD=2.50V
1.23
1.25
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Clock Frequency
freqop
Input Voltage level: 0-2.50V
22
340
MHz
Input Clock Duty Cycle
1
dtin
40
50
60
%
Clock Stabilization
1
tSTAB
from VDD = 2.5V to 1% target frequency
100
( s
1. Guaranteed by design, not 100% tested in production.
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
66 MHz
46
52
63
100 / 125 / 133 MHz
27
33
40
Phase Error
1
tpe
100MHz, input clock 0-2.5V, 0.8ns rise/fall
-113
ps
Output to output Skew
1
Tskew
input clock 0-2.5V, 0.8ns rise/fall
66
98
ps
Low-to-high level Propagation
CLK_IN to any output,
Delay Time, Bypass Mode
1
100MHz, Load = 120 W / 12 pF
Pulse Skew
1
Tskew
ps
Duty Cycle (Sign Ended)
1,3
DC
no loads, 66 MHz to 167MHz
50.2
51.3
%
Rise Time
1
tR
Single-ended 20-80 %; Load=120W/12pF
400
490
622
ps
Fall Time
1
tF
Single-ended 20-80 %; Load=120W/12pF
435
579
711
ps
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting period.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formular: duty_cycle=twH/tC, where the cycle time (tC)decreases as the frequency increases.
Cycle to cycle Jitter
1,2
tc-c
ps
tPLH
3.67
3.68
ns
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