參數(shù)資料
型號: 93AA56
英文描述: 1K/2K/4K 1.8V Microwire Serial EEPROM
中文描述: 1K/2K/4K 1.8V的微型導(dǎo)線串行EEPROM
文件頁數(shù): 8/12頁
文件大?。?/td> 95K
代理商: 93AA56
93AA46/56/66
DS20067G-page 8
1996 Microchip Technology Inc.
3.0
PIN DESCRIPTION
3.1
Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a program cycle,
the device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be LOW for 250 ns minimum (T
CSL
) between
consecutive instructions. If CS is LOW, the internal con-
trol logic is held in a RESET status.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93AAXX.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime with respect to clock HIGH time (T
CKH
) and
clock LOW time (T
CKL
). This gives the controlling mas-
ter freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become don't care
inputs waiting for a new start condition to be detected.
3.3
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
Note:
CS must go LOW between consecutive
instructions.
3.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (T
PD
after the positive
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (T
CSL
) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a pull-
up resistor on DO is required to read the READY signal.
3.5
Organization (ORG)
When ORG is connected to V
CC
, the (x16) memory
organization is selected. When ORG is tied to V
SS
, the
(x8) memory organization is selected. ORG can only be
floated for clock speeds of 1MHz or less for the (x16)
memory organization. For clock speeds greater than 1
MHz, ORG must be tied to V
CC
or V
SS
.
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93AA46 1K/2K/4K 1.8V Microwire Serial EEPROM
93AA46-P 1K/2K/4K 1.8V Microwire Serial EEPROM
93AA46-SM 1K/2K/4K 1.8V Microwire Serial EEPROM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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93AA56-/P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM
93AA56/SM 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K/4K 1.8V Microwire Serial EEPROM
93AA56-/SM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM
93AA56/SN 功能描述:電可擦除可編程只讀存儲器 256x8 Or 128x16 1.8V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8