參數(shù)資料
型號: 93AA86TSN
英文描述: Microwire Serial EEPROM
中文描述: 微型導線串行EEPROM
文件頁數(shù): 6/12頁
文件大?。?/td> 348K
代理商: 93AA86TSN
93AA76/86
DS21130D-page 6
2001 Microchip Technology Inc.
3.0
DEVICE OPERATION
3.1
READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T
PD
). Sequential read is
possible when CS is held high and clock transitions
continue. The memory address pointer will automati-
cally increment and output data sequentially.
3.2
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical
1
state. The self-timed pro-
gramming cycle is initiated on the rising edge of CLK as
the last address bit (A0) is clocked in. At this point, the
CLK, CS, and DI inputs become don
t cares.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical
0
indicates that programming is still in progress. DO at
logical
1
indicates that the register at the specified
address has been erased and the device is ready for
another instruction.
The ERASE cycle takes 3 ms per word (Typical).
3.3
WRITE
The WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the ris-
ing edge of CLK as the last data bit (D0) is clocked in.
At this point, the CLK, CS, and DI inputs become don
t
cares.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical
0
indicates that programming is still in progress. DO at
logical
1
indicates that the register at the specified
address has been written and the device is ready for
another instruction.
The WRITE cycle takes 3 ms per word (Typical).
3.4
Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical
1
state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences on the rising edge of the last address bit (A0).
Note that the least significant 8 or 9 address bits are
don
t care bits, depending on selection of x16 or x8
mode. Clocking of the CLK pin is not necessary after
the device has entered the self clocking mode. The
ERAL instruction is guaranteed at Vcc = +4.5V to
+6.0V.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical
0
indicates that programming is still in progress. DO at
logical
1
indicates that the entire device has been
erased and is ready for another instruction.
The ERAL cycle takes 15 ms maximum (8 ms typical).
3.5
Write All (WRAL)
The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
the least significant 8 or 9 address bits are don
t cares,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL instruction but the chip must be in the EWEN sta-
tus. The WRAL instruction is guaranteed at Vcc =
+4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO
pin to enter the high impedance state. DO at logical
0
indicates that programming is still in progress. DO at
logical
1
indicates that the entire device has been
written and is ready for another instruction.
The WRAL cycle takes 30 ms maximum (16 ms
typical).
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