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參數(shù)資料
| 型號： | 93C46B-SN |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | EEPROM |
| 英文描述： | 1K 5.0V Microwire Serial EEPROM |
| 中文描述： | 一千5.0V微型導(dǎo)線串行EEPROM |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | 93C46B-SN |
93C46B
1997 Microchip Technology Inc.
Preliminary
DS21172D-page 3
2.0
PIN DESCRIPTION
2.1
Chip Select (CS)
A high level selects the device; a low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
CSL
) between
2.2
Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93C46B.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
CKL
). This gives the controlling master
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but START condition has not been
detected, any number of clock cycles can be received
by the device, without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
CKH
) and
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1). CLK and DI then become don't care inputs
waiting for a new START condition to be detected.
2.3
Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out (DO)
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (T
PD
after the posi-
tive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
CSL
) and an ERASE or WRITE operation has
been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
Note:
CS must go low between consecutive
instructions.
TABLE 2-1
INSTRUCTION SET FOR 93C46B
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1
11
A5
A4
A3
A2
A1
A0
—
(RDY/BSY)
9
1
00
1
0
X
X
X
X
—
(RDY/BSY)
9
1
00
0
0
X
X
X
X
—
HIGH-Z
9
1
00
1
1
X
X
X
X
—
HIGH-Z
9
1
10
A5
A4
A3
A2
A1
A0
—
D15 - D0
25
1
01
A5
A4
A3
A2
A1
A0
D15 - D0
(RDY/BSY)
25
1
00
0
1
X
X
X
X
D15 - D0
(RDY/BSY)
25
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| 93C56B | 2K 5.0V Automotive Temperature Microwire Serial EEPROM |
| 93C56BEP | 2K 5.0V Automotive Temperature Microwire Serial EEPROM |
| 93C56BESN | 2K 5.0V Automotive Temperature Microwire Serial EEPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 93C46B-ST | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K 5.0V Microwire Serial EEPROM |
| 93C46BT-/SM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| 93C46BT/SN | 功能描述:電可擦除可編程只讀存儲器 64x16 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 93C46BT-/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
| 93C46BT/SN-CUT TAPE | 制造商:Microchip 功能描述:93C46 Series 1 Kbit (64 x 16) 5.5 V Microwire Compatible Serial EEPROM - SOIC-8 |
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