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參數(shù)資料
| 型號： | 93C66AXTIOT |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | EEPROM |
| 英文描述： | 4K Microwire Compatible Serial EEPROM |
| 中文描述： | 4K的微絲兼容串行EEPROM |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 405K |
| 代理商： | 93C66AXTIOT |
2003 Microchip Technology Inc.
DS21795B-page 7
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.5
ERASE ALL (ERAL)
The Erase All (
ERAL
) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
).
Note:
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
V
CC
must be
≥
4.5V for proper operation of ERAL.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
0
0
1
0
X
X
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
EC
HIGH-Z
V
CC
must be
≥
4.5V for proper operation of ERAL.
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
0
0
1
0
X
X
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
EC
HIGH-Z
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 93C66AXTIOTG | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K Microwire Compatible Serial EEPROM |
| 93C66AXTIP | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K Microwire Compatible Serial EEPROM |
| 93C66AXTIPG | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K Microwire Compatible Serial EEPROM |
| 93C66AXTISN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K Microwire Compatible Serial EEPROM |
| 93C66AXTISNG | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4K Microwire Compatible Serial EEPROM |
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