參數(shù)資料
型號(hào): 93C66BIPG
廠商: Microchip Technology Inc.
英文描述: PV74W20-39P
中文描述: 4K的微絲兼容串行EEPROM
文件頁數(shù): 21/24頁
文件大?。?/td> 405K
代理商: 93C66BIPG
93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795B-page 6
2003 Microchip Technology Inc.
2.4
ERASE
The ERASE instruction forces all data bits of the speci-
fied address to the logical ‘1’ state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
FIGURE 2-1:
ERASE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
CS
CLK
DI
DO
TCSL
CHECK STATUS
1
1AN
AN-1
AN-2
A0
TSV
TCZ
BUSY
READY
HIGH-Z
TWC
HIGH-Z
CS
CLK
DI
DO
TCSL
CHECK STATUS
1
1AN
AN-1
AN-2
A0
TSV
TCZ
BUSY
READY
HIGH-Z
TWC
HIGH-Z
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