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參數(shù)資料
| 型號(hào)： | 93L00FMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | 4-Bit Universal Shift Register |
| 中文描述： | 93 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16 |
| 封裝： | CERAMIC, FP-16 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | 93L00FMQB |
Functional Description
The Logic Diagrams and Truth Table indicate the functional
characteristics of the 93L00 4-bit shift register. The device is
useful in a wide variety of shifting, counting and storage
applications. It performs serial, parallel, serial-to-parallel, or
parallel-to-serial data transfers.
The 93L00 has two primary modes of operation, shift right
(Q0
Q1) and parallel load, which are controlled by the
state of the Parallel Enable (PE) input. When the PE input is
HIGH, serial data enters the first flip-flop Q0 via the J and K
inputs
and
is
one
Q0
Q1
x
Q2
x
Q3
following
clock transition. The JK inputs provide the flexibility of the
JK type input for special applications, and the simple D-type
input for general applications by tying the two pins together.
bit
in
the
LOW-to-HIGH
direction
each
When the PE input is LOW, the 93L00 appears as four com-
mon clocked D flip-flops. The data on the parallel inputs
P0–P3 is transferred to the respective Q0–Q3 outputs fol-
lowing the LOW-to-HIGH clock transition. Shift left opera-
tion (Q3
Q2) can be achieved by tying the Qn outputs to
the Pn
b
1 inputs and holding the PE input LOW.
All serial and parallel data transfers are synchronous, occur-
ing after each LOW-to-HIGH clock transition. Since the
93L00 utilizes edge triggering, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operationDex-
cept for the setup and release time requirements. A LOW on
the asynchronous Master Reset (MR) input sets all Q out-
puts LOW, independent of any other input condition.
Truth Table
Operating
Mode
Inputs (MR
e
H)
Outputs
@
t
n
a
1
PE
J
K
P0
P1
P2
P3
Q0
Q1
Q2
Q3
Q3
H
H
H
H
L
L
H
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Shift Mode
Q0
Q0
H
Parallel
Entry Mode
L
L
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
L
*
t
n
a
1
e
Indicates state after next LOW-to-HIGH clock transition.
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
4
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