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參數(shù)資料
| 型號(hào)： | 93L38 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 127K |
| 代理商： | 93L38 |
Switching Characteristics
V
CC
e a
5.0V, T
A
e a
25
§
C (See Section 1 for Test Waveforms and Output Load
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
t
PHL
Propagation Delay
B
n
or C
n
or Z
n
68
95
ns
t
PLH
t
PHL
Propagation Delay
D
A
to Z
n
70
92
ns
t
PLH
t
PHL
Propagation Delay
CP to Z
n
65
57
ns
Functional Description
The 93L38 8-bit multiple port register can be considered a
1-bit slice of eight high speed working registers. Data can be
written into any one and read from any two of the eight
locations simultaneously. Master/slave operation eliminates
all race problems associated with simultaneous read/write
activity from the same location. When the clock input (CP) is
LOW data applied to the data input line (D
A
) enters the
selected master. This selection is accomplished by coding
the three write input select lines (A0–A2) appropriately.
Data is stored synchronously with the rising edge of the
clock pulse.
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0–B2 and
C0–C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (Z
B
and Z
C
).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The data
flows into the device, is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch. The eight latches function as masters and store the
input data. The two output latches are slaves and hold the
data during the read operation. The state of each slave is
determined by the state of the master selected by its associ-
ated set of read address inputs.
The method of parallel expansion is shown inFigure A. One
93L38 is needed for each bit of the required word length.
The read and write input lines should be connected in com-
mon on all of the devices. This register configuration pro-
vides two words of n-bits each at one time, where n devices
are connected in parallel.
TL/F/10202–4
FIGURE A. Parallel Expansion
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 93L38 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 93L38DC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| 93L38DMQB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| 93L38FMQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Multiple Port Register |
| 93L38PC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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