參數(shù)資料
型號: 93LC46A
廠商: Microchip Technology Inc.
元件分類: EEPROM
英文描述: 1K 2.5V Microwire Serial EEPROM
中文描述: 一千2.5V的微型導(dǎo)線串行EEPROM
文件頁數(shù): 7/12頁
文件大?。?/td> 203K
代理商: 93LC46A
93LC46A/B
1997 Microchip Technology Inc.
Preliminary
DS21173D-page 7
3.8
WRITE
The WRITE instruction is followed by 8 bits (93LC46A)
or 16 bits (93LC46B) of data which are written into the
specified address. After the last data bit is put on the DI
pin, the falling edge of CS initiates the self-timed auto-
erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire write cycle is complete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
3.9
Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
FIGURE 3-7:
WRITE TIMING
FIGURE 3-8:
WRAL TIMING
CS
CLK
DI
DO
1
0
1
An
A0
Dx
D0
BUSY
READY
HIGH-Z
HIGH-Z
Twc
T
CSL
T
CZ
T
SV
CS
CLK
DI
DO
HIGH-Z
1
0
0
0
1
X
X
Dx
D0
HIGH-Z
BUSY
READY
T
WL
Guaranteed at Vcc = 4.5V to +6.0V.
T
CSL
T
SV
T
CZ
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