參數(shù)資料
型號(hào): 93LC46T-I/MS
元件分類: PROM
英文描述: 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封裝: PLASTIC, MSOP-8
文件頁(yè)數(shù): 17/20頁(yè)
文件大?。?/td> 510K
代理商: 93LC46T-I/MS
93XX46, 93XX46A/B
DS21749A-page 6
2002 Microchip Technology Inc.
2.4
ERASE
The ERASE instruction forces all data bits of the speci-
fied address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
ming cycle, except on ‘C’ devices where the rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
FIGURE 2-1:
ERASE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
1A
N
A
N-1
A
N-2
A0
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
WC
HIGH-Z
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
1A
N
A
N-1
A
N-2
A0
T
SV
T
CZ
BUSY
READY
HIGH-Z
T
WC
HIGH-Z
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