參數(shù)資料
型號: 93V850DGT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 93V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 0.240 INCH, MO-153, TSSOP-48
文件頁數(shù): 1/10頁
文件大?。?/td> 194K
代理商: 93V850DGT
Integrated
Circuit
Systems, Inc.
ICS93V850
Preliminary Product Preview
0423H—07/03/03
Block Diagram
DDR Phase Lock Loop Clock Driver
Pin Configuration
48-Pin TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
I
2C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
With bypass mode mux
Operating frequency 60 to 140 MHz
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<120ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Slew Rate: 1V/ns - 2V/ns
Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
AVDD
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
P
D
V
AT
N
I
_
K
L
CC
N
I
_
K
L
CT
K
L
CC
K
L
CT
T
U
O
_
B
FC
T
U
O
_
B
F
D
N
GL
H
L
H
L
H
f
O
/
d
e
s
a
p
y
B
D
N
GH
L
H
L
H
L
f
O
/
d
e
s
a
p
y
B
V
5
.
2
)
m
o
n
(
LH
L
H
L
H
n
O
V
5
.
2
)
m
o
n
(
HL
H
L
H
L
n
O
V
5
.
2
)
m
o
n
(
z
H
M
0
2
<z
H
M
0
2
<Z
-
i
HZ
-
i
HZ
-
i
HZ
-
i
Hf
f
O
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
CLK_INC
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
VDDI C
2
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
CLKC7
CLKT7
VDD
SDATA
FB_INC
VDD
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
FB_INT
FB_OUTC
ICS93V850
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
相關(guān)PDF資料
PDF描述
93V855AGLFT 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
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93V855AG 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
93V855AGI 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
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