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參數(shù)資料
| 型號(hào)： | 93V855AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93V SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, GREEN, MO-153, TSSOP-28 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | 93V855AGLF |
5
ICS93V855I
0783C—06/01/04
Switching Characteristics
TA = -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Max clock frequency
3
freqop
33
233
MHz
Application Frequency
Range
3
freqApp
60
170
MHz
Input clock duty cycle
dtin
40
60
%
Output clock slew rate
tsl(o)
12
v/ns
CLK stabilization
TSTAB
100
s
Low-to high level propagation
delay time
tPLH
1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
tPHL
1
CLK_IN to any output
5.5
ns
Output enable time
ten
PD# to any output
5
ns
Output disable time
tdis
PD# to any output
5
ns
Period jitter
tjit (per)
-75
75
ps
Half-period jitter
tjit(hper)
-100
100
ps
Input clock slew rate
tsl(I)
12
v/ns
Cycle to Cycle Jitter
tcyc-tcyc
-75
75
ps
Phase error
4
t(phase error)
-50
50
ps
Output to Output Skew
tskew
40
60
ps
Rise Time, Fall Time
tr, tf
Load = 120
/16pF
650
800
950
ps
Over the application
frequency range
Notes:
1.
2.
3.
4. Does not include jitter.
Switching characteristics are guaranteed for application frequency range. The PLL
Locks over the Max Clock Frequency range, but the device doe not necessarily
meet other timing parameters.
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
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