參數(shù)資料
型號(hào): 94228BFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 233.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, LEAD FREE, MO-118, SSOP-48
文件頁(yè)數(shù): 19/19頁(yè)
文件大小: 189K
代理商: 94228BFLF
9
ICS94228
0447E—05/07/04
Byte 13: Output Skew Control Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
l
o
r
t
n
o
C
w
e
k
S
0
T
/
0
C
K
L
C
U
P
C
6
t
i
B-
0
5
t
i
B-
0
4
t
i
B-
0
3
t
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B-
0
l
o
r
t
n
o
C
w
e
k
S
C
/
T
S
C
_
C
K
L
C
U
P
C
2
t
i
B-
0
1
t
i
B-
0
t
i
B-
0
Byte 14: Output Skew Control Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
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B-
0
l
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C
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0
:
8
(
K
L
C
I
C
P
6
t
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B-
0
5
t
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B-
1
4
t
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B-
0
3
t
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B-
0
l
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C
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S
)
0
:
2
(
P
G
A
2
t
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B-
0
1
t
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B-
0
l
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C
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t
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R
w
e
l
S
:
E
_
9
K
L
C
I
C
P
0
t
i
B-
0
Byte 15: Output Rise/Fall Time Select Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
T
K
L
C
U
P
C
6
t
i
B-
0
C
K
L
C
U
P
C
5
t
i
B-
0
T
S
C
_
T
K
L
C
U
P
C
4
t
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B-
0
C
S
C
_
C
K
L
C
U
P
C
3
t
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B-
1
l
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r
t
n
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C
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t
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:
)
0
:
2
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A
2
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0
1
t
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B-
0
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C
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t
a
R
w
e
l
S
:
)
0
:
2
(
F
E
R
0
t
i
B-
0
Byte 16: Output Rise/Fall Time Select Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
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B-
0
l
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n
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C
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t
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R
w
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l
S
:
)
0
:
3
(
K
L
C
I
C
P
6
t
i
B-
0
5
t
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B-
1
l
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n
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C
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t
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R
w
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l
S
:
)
4
:
8
(
K
L
C
I
C
P
4
t
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B-
0
3
t
i
B-
0
l
o
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t
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o
C
e
t
a
R
w
e
l
S
:
z
H
M
8
4
2
t
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0
1
t
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B-
0
l
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o
C
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t
a
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w
e
l
S
:
z
H
M
8
4
_
4
2
0
t
i
B-
0
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