參數(shù)資料
型號(hào)： 951200201
廠商： ATMEL CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： 40-BIT, DSP-FLOATING POINT PROCESSOR, QFP256
封裝： MQFP-256
文件頁(yè)數(shù)： 39/50頁(yè)
文件大?。?/td> 702K
代理商： 951200201
44
TSC21020F
4153H–AERO–04/07
4) their voltage swing (VDD).
It is calculated by:
PEXT = O x C x VDD
2 x f
The load capacitance should include the processor's package capacitance (CIN). The
switching frequency includes driving the load high and then back low. Address and data
pins can drive high and low at a maximum rate of 1/(2tCK). The write strobes can switch
every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but 2 DM and 2 PM
selects can switch on each cycle. If only one bank is accessed, no select line will switch.
For instance, the maximum power dissipation will be:
PINT Max = IDDINMax x VDDMax = 0,430 x 5,5 = 2,36W
PEXT Max = 0 x C x VDD Max
2 x f
= 164 x 10-11 x 5.52 x 20.106 = 0.99W
Pmax = 3.4W
Power and Ground Guidelines
To achieve its fast cycle time, including instruction fetch, data access, and execution,
the TSC21020F is designed with high speed drivers on all output pins. Large peak cur-
rents may pass through a circuit board's ground and power lines, especially when many
output drivers are simultaneously charging or discharging their load capacitances.
These transient currents can cause disturbances on the power and ground lines. To
minimize these effects, the TSC21020F provides separate supply pins for its internal
logic (IGND and IVDD) and for its external drivers (EGND and EVDD).
All GND pins should have a low impedance path to ground. A ground plane is required
in TSC21020F systems to reduce this impedance, minimizing noise.
The EVDD and IVDD pins should be bypassed to the ground plane using approximately
14 high-frequency capacitors (0.1 F ceramic). Keep each capacitor's lead and trace
length to the pins as short as possible. This low inductive path provides the TSC21020F
with the peak currents required when its output drivers switch. The capacitors' ground
leads should also be short and connect directly to the ground plane. This provides a low
impedance return path for the load capacitance of the TSC21020F's output drivers.
If a VDD plane is not used, the following recommendations apply. Traces from the + 5V
supply to the 10 EVDD pins should be designed to satisfy the minimum VDD specifica-
tion while carrying average dc currents of [IDDEX/10 x (number of EVDD pins per trace)].
IDDEX is the calculated external supply current. A similar calculation should be made for
the four IVDD pins using the IDDIN specification. The traces connecting +5V to the IVDD
pins should be separate from those connecting to the EVDD pins.
Pin Type
# Pins
% Switch
xC
xf
xVDD
2
PEXT
PMA
PMS
PMWR
PMD
DMA
DMS
DMWR
DMD
15
2
1
32
15
2
1
32
50
0
-
50
0
-
50
68 pF
18 pF
48 pF
18 pF
5 MHz
10 MHz
5 MHz
10 MHz
5 MHz
25V
0.064W
0.000W
0.017W
0.036W
0.045W
0.000W
0.012W
0.036W
PEXT = 0.210W
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