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參數(shù)資料
| 型號： | 9763-11 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, CQCC68 |
| 封裝： | CERAMIC, QFJ-68 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 351K |
| 代理商： | 9763-11 |
Product Specification
PE9763
Page 3 of 15
Document No. 70-0140-02
│ www.psemi.com
2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Pin No.
Pin
Name
Valid
Mode
Type
Description
16
K7
Direct
Input
K Counter bit7.
17
K8
Direct
Input
K Counter bit8.
18
K9
Direct
Input
K Counter bit9.
19
K10
Direct
Input
K Counter bit10.
20
K11
Direct
Input
K Counter bit11.
21
K12
Direct
Input
K Counter bit12.
22
K13
Direct
Input
K Counter bit13.
23
K14
Direct
Input
K Counter bit14.
24
K15
Direct
Input
K Counter bit15.
25
K16
Direct
Input
K Counter bit16.
26
K17
Direct
Input
K Counter bit17 (MSB).
27
VDD
(Note 1)
Digital core VDD.
VDD
(Note 1)
ESD VDD.
28
GND
Downbond
Digital core ground.
GND
Downbond
ESD ground.
29
M0
Direct
Input
M Counter bit0 (LSB).
30
M1
Direct
Input
M Counter bit1.
31
M2
Direct
Input
M Counter bit2
32
M3
Direct
Input
M Counter bit3.
33
M4
Direct
Input
M Counter bit4.
S_WR
Serial
Input
Serial load enable input. While S_WR is “l(fā)ow”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
34
M5
Direct
Input
M Counter bit5.
SDATA
Serial
Input
Binary serial data input. Input data entered MSB first.
35
M6
Direct
Input
M Counter bit6.
SCLK
Serial
Input
Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “l(fā)ow”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
36
M7
Direct
Input
M Counter bit7.
37
M8
Direct
Input
M Counter bit8 (MSB).
38
A0
Direct
Input
A Counter bit0 (LSB).
39
A1
Direct
Input
A Counter bit1.
E_WR
Serial
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
40
A2
Direct
Input
A Counter bit2.
41
A3
Direct
Input
A Counter bit3 (MSB).
42
DIRECT
Both
Input
Direct mode select. “High” enables direct mode. “Low” enables serial mode.
43
Pre_en
Direct
Input
Prescaler enable, active “l(fā)ow”. When “high”, Fin bypasses the prescaler.
44
VDD
(Note 1)
Digital core VDD.
45
GND
Downbond
Digital core ground.
GND
Downbond
ESD ground.
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