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參數(shù)資料
| 型號： | 97ULPA877AHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-225/205, VFBGA-52 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 183K |
| 代理商： | 97ULPA877AHLF-T |
12
ICS97ULPA877A
1088B—01/18/06
Figure 11. AVDD Filtering
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
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