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參數(shù)資料
| 型號： | 9883 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Umnmanaged Repeater |
| 中文描述： | 高級10/100 Umnmanaged直放站 |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 719K |
| 代理商： | 9883 |
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Advanced 10/100 Unmanaged Repeater
—
LXT9883/9863
Datasheet
Document #: 249115
Revision #: 003
Rev. Date: 08/07/01
19
3.4
Repeater Operation
The LXT98x3 contains two internal repeater state machines
—
one operating at 10 Mbps and the
other at 100 Mbps. The LXT98x3 automatically switches each port to the correct repeater, once the
operational state of that port has been determined. Each repeater connects all ports configured to
the same speed (including the MII), and the corresponding Inter-Repeater Backplane. Both
repeaters perform the standard jabber and partition functions.
3.4.1
100 Mbps Repeater Operation
The LXT98x3 contains a complete 100 Mbps Repeater State Machine (100RSM) that is fully IEEE
802.3 Class II compliant. Any port configured for 100 Mbps operation is automatically connected
to the 100 Mbps Repeater. This includes any of the eight media and two MII ports configured for
100 Mbps operation.
The 100 Mbps RSM has its own Inter-Repeater Backplane (100IRB). Multiple LXT98x3s can be
cascaded on the 100IRB and operate as one repeater segment. Data from any port is forwarded to
all other ports in the cascade. The 100IRB is a 5-bit symbol-mode interface. It is designed to be
stackable.
The LXT98x3 performs the following 100 Mbps repeater functions:
Signal amplification, wave-shape restoration, and data-frame forwarding.
SOP, SOJ, EOP, EOJ delay < 46BT; class II compliant.
Collision Enforcement. During a 100 Mbps collision, the LXT98x3 drives a 0101 jam signal
(encoded as Data 5 on TX links) to all ports until the collision ends. There is no minimum
enforcement time.
Partition. The LXT98x3 partitions any port that participates in excess of 60 consecutive
collisions or one long collision approximately 575.2
μ
s long. Once partitioned, the LXT98x3
monitors and transmits to the port, but does not repeat data received from the port until it un-
partitions.
Figure 4. MII Interface
MAC
TXD(3:0)
TXEN
TXER
TXCLK
RXCLK
RXD(3:0)
LXT98x3
RX_DV
RX_ER
CRS
COL
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