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參數(shù)資料
| 型號： | 9DB102AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 223K |
| 代理商： | 9DB102AGLF |
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Revision History
Rev.
Issue Date Description
Page #
F
8/6/2007
1. Added Phase Noise Parameters, Updated input to output delay values.
2. PLL BW moved to PLL parameters table.
3. Added terminations tables.
Various
G
12/14/2007 Updated General SMBus Interface Information.
8
H
10/29/2008 Corrected "HCSL" typos.
1, 6, 7
J
1/15/2010
1. Added I-temp electricals
2. Changed datasheet title
3. Updated Input Frequency parameter
4. Updated ordering information
Various
相關PDF資料 |
PDF描述 |
|---|---|
| 9DB102AFLFT | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AFLF | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102AGLFT | PLL BASED CLOCK DRIVER, PDSO20 |
| 9DB102BFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB102BGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB102BFILF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Two Output Differential Buffer for PCIe Gen1 & Gen2 |
| 9DB102BFILFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Two Output Differential Buffer for PCIe Gen1 & Gen2 |
| 9DB102BFLF | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB102BFLFT | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB102BGILF | 功能描述:時鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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