參數(shù)資料
型號(hào): 9DB102BFILFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 0.150 INCH, ROHS COMPLIANT, SSOP-20
文件頁(yè)數(shù): 9/13頁(yè)
文件大?。?/td> 150K
代理商: 9DB102BFILFT
IDT
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV N 04/20/11
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
5
Electrical Characteristics - PLL Parameters
TA = Tambient; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
Min
Typ
Max
Units
Notes
PLL Jitter Peaking
jpeak-hibw
(PLL_BW = 1)
0
1
2.5
dB
1,4
PLL Jitter Peaking
jpeak-lobw
(PLL_BW = 0)
0
1
2
dB
1,4
PLL Bandwidth
pllHIBW
(PLL_BW = 1)
2
2.5
3
MHz
1,5
PLL Bandwidth
pllLOBW
(PLL_BW = 0)
0.4
0.5
1
MHz
1,5
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
40
108
ps
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
2.7
3.1
ps rms
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
2.2
3.1
ps rms
1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
1.3
3
ps rms
1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
Jitter, Phase
tjphasePLL
相關(guān)PDF資料
PDF描述
9DB102BGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB102BGILF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB102BGLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB102BFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
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