參數(shù)資料
型號(hào)： 9DB102BGILFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝： 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20
文件頁(yè)數(shù)： 6/13頁(yè)
文件大?。?/td> 150K
代理商： 9DB102BGILFT
IDT
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV N 04/20/11
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
2
Pin Configuration
20-pin SSOP & TSSOP
VDD
GND
5,9,12,16
6,15
PCI Express Outputs
96
SMBUS
20
19
IREF
20
19
Analog VDD & GND for PLL core
Description
Pin Number
Power Groups
Pin Description
PLL_BW 1
20 VDDA
CLK_INT 2
19 GNDA
C LK_INC 3
18 IREF
vCLKREQ0# 4
17 vC LKREQ1#
VDD 5
16 VDD
GND 6
15 GND
PCIEXT0 7
14 PCIEXT1
PCIEXC0 8
13 PCIEXC1
VDD 9
12 VDD
SMBDAT 10
11 SMBCLK
IC
S
9
DB
1
0
2
Note: Pins preceeded by ' v ' have internal
120K ohm pull down resistors
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
PLL_BW
IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2
CLK_INT
IN
True Input for differential reference clock.
3
CLK_INC
IN
Complementary Input for differential reference clock.
4
v CLKREQ0#
IN
Output enable for PCI Expres s output pair 0.
0 = enabled, 1 =disabled
5
VDD
PWR
Power supply , nominal 3.3V
6
GND
PWR
Ground pin.
7
PCIEXT0
OUT
True clock of differential PCI_Express pair.
8
PCIEXC0
OUT
Complementary clock of differential PCI_Express pair.
9
VDD
PWR
Power supply , nominal 3.3V
10
SMBDAT
I/O
Data pin of SMBUS c ircuitry, 5V tolerant
11
SMBCLK
IN
Clock pin of SMBUS c ircuitry, 5V tolerant
12
VDD
PWR
Power supply , nominal 3.3V
13
PCIEXC1
OUT
Complementary clock of differential PCI_Express pair.
14
PCIEXT1
OUT
True clock of differential PCI_Express pair.
15
GND
PWR
Ground pin.
16
VDD
PWR
Power supply , nominal 3.3V
17
v CLKREQ1#
IN
Output enable for PCI Expres s output pair 1.
0 = enabled, 1 =disabled
18
IREF
OUT
This pin establishes the reference for the differential current-mode
output pairs. It requires a fix ed precision resistor to ground. 475ohm is
the standard value for 100ohm differential impedance. Other
impedanc es require different values. See data sheet.
19
GNDA
PWR
Ground pin for the PLL c ore.
20
VDDA
PWR
3.3V power for the PLL core.
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
Note:
相關(guān)PDF資料
PDF描述
9DB102BGILF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB102BGLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB102BFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB106BFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB106BFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB102BGLF 功能描述:時(shí)鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB102BGLFT 功能描述:時(shí)鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB104BFLF 功能描述:時(shí)鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB104BFLFT 功能描述:時(shí)鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB104BFLNT 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL UP TO 200MHZ 28SSOP - Tape and Reel
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