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參數(shù)資料
| 型號： | 9DB102BGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 150K |
| 代理商： | 9DB102BGLF |
IDT
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV N 04/20/11
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
9
SMB us Table: Device C ontrol Register, READ/WRITE ADDR ESS (D4/D5)
Pin #
Name
Control Function Type
0
1
PWD
Bit 7
SW_EN
Enables SMBus
Control
RW
Functions
controlled by
SMBus
registers
Functions
controlled by
device pins
1
Bit 6
RW
X
Bit 5
RW
X
Bit 4
RW
X
Bit 3
RW
X
Bit 2
RW
X
Bit 1
PLL BW #adjust
Selects PLL
Bandwidth
R W
Low BW
High BW
1
Bit 0
PLL Enable
Bypasses PLL for
board test
RW
PLL bypassed
(fan out mode)
PLL enabled
(ZDB mode)
1
SMB us Table: Output Enable Register
Pin #
Name
Control Function Type
0
1
PWD
Bit 7
RW
X
Bit 6
RW
X
Bit 5
RW
X
Bit 4
RW
X
Bit 3
RW
X
Bit 2
RW
X
Bit 1
RW
X
Bit 0
RW
X
SMB us Table: Function Select Register
Pin #
Name
Control Function Type
0
1
PWD
Bit 7
R W
X
Bit 6
R W
X
Bit 5
R W
X
Bit 4
R W
X
Bit 3
R W
X
Bit 2
R W
X
Bit 1
R W
X
Bit 0
RW
X
SMB us Table: Vendor & Revision ID Register
Pin #
Name
Control Function Type
0
1
PWD
Bit 7
RID3
R
-
0
Bit 6
RID2
R
-
0
Bit 5
RID1
R
-
0
Bit 4
RID0
R
-
1
Bit 3
VID 3
R
-
0
Bit 2
VID 2
R
-
0
Bit 1
VID 1
R
-
0
Bit 0
VID 0
R
-
1
RESERVED
-
RESERVED
-
RESERVED
-
Byte 3
-
Byte 2
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
Byte 1
-
RESERVED
-
RESERVED
REVISION ID
VENDOR ID
Byte 0
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
RESERVED
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB102BFILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB102BGILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB102BGILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB102BGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 9DB102BFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB102BGLFT | 功能描述:時(shí)鐘緩沖器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB104BFLF | 功能描述:時(shí)鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB104BFLFT | 功能描述:時(shí)鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB104BFLNT | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL UP TO 200MHZ 28SSOP - Tape and Reel |
| 9DB104BFT | 制造商:INT CIR SYS 功能描述: |
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