參數(shù)資料
型號： 9DB1233AGLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù)： 10/15頁
文件大?。?/td> 181K
代理商： 9DB1233AGLF
IDT Twelve Output Differential Buffer for PCIe Gen3
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
4
1675B—11/08/10
Pin Description (cont.)
PIN #
PIN NAME
TYPE
DESCRIPTION
33
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
34
GND
PWR
Ground pin.
35
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
36
VTTPWRGD#/PD
IN
VTTPWRGD# is an active low input used to sample latched inputs and
allow the device to Power Up. PD is an asynchronous active high input
pin used to put the device into a low power state. The internal clocks and
PLLs are stopped.
37
DIF_6#
OUT
0.7V differential Complementary clock output
38
DIF_6
OUT
0.7V differential true clock output
39
OE6#
IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
40
GND
PWR
Ground pin.
41
VDD
PWR
Power supply, nominal 3.3V
42
DIF_7#
OUT
0.7V differential Complementary clock output
43
DIF_7
OUT
0.7V differential true clock output
44
OE7#
IN
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
45
DIF_8#
OUT
0.7V differential Complementary clock output
46
DIF_8
OUT
0.7V differential true clock output
47
OE8#
IN
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
48
VDD
PWR
Power supply, nominal 3.3V
49
GND
PWR
Ground pin.
50
DIF_9#
OUT
0.7V differential Complementary clock output
51
DIF_9
OUT
0.7V differential true clock output
52
OE9#
IN
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
53
DIF_10#
OUT
0.7V differential Complementary clock output
54
DIF_10
OUT
0.7V differential true clock output
55
OE10#
IN
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
56
GND
PWR
Ground pin.
57
VDD
PWR
Power supply, nominal 3.3V
58
DIF_11#
OUT
0.7V differential Complementary clock output
59
DIF_11
OUT
0.7V differential true clock output
60
OE11#
IN
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
61
VDD
PWR
Power supply, nominal 3.3V
62
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
63
AGND
PWR
Analog Ground pin for Core PLL
64
VDDA
PWR
3.3V power for the PLL core.
相關(guān)PDF資料
PDF描述
9DB1904BKLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
9DB1933AKLF 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
9DB1933AKLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
9DB202CGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB202CFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB1233AGLFT 功能描述:時鐘緩沖器 12 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1904B 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:19 Output Differential Buffer for PCIe Gen2 and QPI
9DB1904BKLF 功能描述:時鐘緩沖器 19 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1904BKLFT 功能描述:時鐘緩沖器 19 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB1933 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Nineteen Output Differential Buffer for PCIe Gen3
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