參數(shù)資料
型號(hào)： 9DB433AFLIFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝： 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 190K
代理商： 9DB433AFLIFT
IDT
Four Output Differential Buffer for PCIe Gen 3
1658B - 05/09/11
9DB433
Four Output Differential Buffer for PCIe Gen 3
3
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1VDDR
PWR
3.3V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
2
SRC_IN
IN
0.7 V Differential SRC TRUE input
3
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
4
GND
PWR
Ground pin.
5
VDD
PWR
Power supply, nominal 3.3V
6
DIF_1
OUT
0.7V differential true clock output
7
DIF_1#
OUT
0.7V differential Complementary clock output
8OE1#
IN
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
9
DIF_2
OUT
0.7V differential true clock output
10
DIF_2#
OUT
0.7V differential Complementary clock output
11
VDD
PWR
Power supply, nominal 3.3V
12
BYP#_HIBW_LOBW
IN
Tri-level input to select bypass mode, Hi BW PLL, or Lo BW PLL mode
13
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
14
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
15
GND
PWR
Ground pin.
16
VDD
PWR
Power supply, nominal 3.3V
17
SMB_ADR_tri
IN
SMBus address select bit. This is a tri-level input that decodes 1 of 3 SMBus
Addresses.
18
VDD
PWR
Power supply, nominal 3.3V
19
DIF_5#
OUT
0.7V differential Complementary clock output
20
DIF_5
OUT
0.7V differential true clock output
21
OE6#
IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
22
DIF_6#
OUT
0.7V differential Complementary clock output
23
DIF_6
OUT
0.7V differential true clock output
24
VDD
PWR
Power supply, nominal 3.3V
25
PD#
IN
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
26
IREF
OUT
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.
相關(guān)PDF資料
PDF描述
9DB433AGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB433AFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB633AFLIFT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB633AGILF 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB633AFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB433AGILF 功能描述:時(shí)鐘緩沖器 4 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB433AGILFT 功能描述:鎖相環(huán) - PLL 4 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
9DB433AGLF 功能描述:時(shí)鐘緩沖器 4 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB433AGLFT 功能描述:時(shí)鐘緩沖器 4 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB633 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Six Output Differential Buffer for PCIe Gen3
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