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參數(shù)資料
| 型號： | 9EPRS475CGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 177K |
| 代理商： | 9EPRS475CGLFT |
IDT
System Clock for Embedded AMDTM based Systems
1615B—04/26/10
9EPRS475
System Clock for Embedded AMDTM based Systems
11
SMBus Table:Test Mode Register
Byte
15
Name
Control Function
Type
0
1
Default
Bit 7
Test_Md_Sel
Selects Test Mode
RW
Normal mode
All ouputs are REF/N
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: CPU PLL Frequency Control Register
Byte
16
Name
Control Function
Type
0
1
Default
Bit 7
N Div2
N Divider Prog bit 2
RW
X
Bit 6
N Div1
N Divider Prog bit 1
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
SMBus Table: CPU PLL Frequency Control Register
Byte
17
Name
Control Function
Type
0
1
Default
Bit 7
N Div10
RW
X
Bit 6
N Div9
RW
X
Bit 5
N Div8
RW
X
Bit 4
N Div7
RW
X
Bit 3
N Div6
RW
X
Bit 2
N Div5
RW
X
Bit 1
N Div4
RW
X
Bit 0
N Div3
RW
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte
18
Name
Control Function
Type
0
1
Default
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
SB_SRC_Ssel
SB_SRC PLL Source Selection (MSB)
RW
10 - N/A
11 - CPU PLL
0
Bit 2
ATIG_Ssel
ATIGCLK PLL Source Selection
RW
SRC PLL
FIX PLL
0
Bit 1
SRC_Ssel
SRC PLL Source Selection
RW
SRC PLL
FIX PLL
0
Bit 0
SB_SRC_Ssel
SB_SRC PLL Source Selection (LSB)
RW
00 - SRC PLL
01 - FIX PLL
0
SMBus Table: Reserved
Byte
19
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
The decimal representation of M and N Divider in
Byte 16 and 17 will configure the VCO frequency.
Default at power up = Byte 0 Rom table. See M/N
Caculation Tables for VCO frequency formulas.
M Divider Programming bits
N Divider Programming b(10:3)
The decimal representation of M and N Divider in
Byte 16 and 17 will configure the VCO frequency.
Default at power up = Byte 0 Rom table. See M/N
Caculation Tables for VCO frequency formulas.
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9EPRS488CKLF | 功能描述:時鐘合成器/抖動清除器 Embedded 72P CLK f/ AMD Based System RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9EPRS488CKLFT | 功能描述:時鐘合成器/抖動清除器 Embedded 72P CLK f/ AMD Based System RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9EPRS525AGILF | 功能描述:時鐘合成器/抖動清除器 EMBEDDED 56P CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9EPRS525AGILFT | 功能描述:時鐘合成器/抖動清除器 EMBEDDED 56P CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9EPRS525AGLF | 功能描述:時鐘合成器/抖動清除器 EMBEDDED 56P CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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