參數(shù)資料
型號(hào): 9EPRS525AGILF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁數(shù): 2/20頁
文件大?。?/td> 210K
代理商: 9EPRS525AGILF
IDTTM
56-pin CK505 for Embedded Intel Systems
1614B—01/21/10
ICS9EPRS525
10
56-pin CK505 for Embedded Systems
FSLC
2
B0b7
FSLB
1
B0b6
FSLA
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
266.66
0
1
133.33
0
1
0
200.00
0
1
166.66
1
0
333.33
1
0
1
100.00
1
0
400.00
111
1. FS
LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
LC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 1: CPU Frequency Select Table
Reserved
100.00
33.33 14.318 48.00 96.00
Pin 17 Pin 18
Spread
MHz
%
00
0
1
100.00 100.00 0.5% Down Spread
SRC clocks from SRC_MAIN
0
1
0
100.00 100.00 0.5% Down Spread
Only SRCCLK1 from PLL3
0
1
100.00 100.00
1% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00 100.00 1.5% Down Spread
Only SRCCLK1 from PLL3
0
1
0
1
100.00 100.00
2% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00 100.00 2.5% Down Spread
Only SRCCLK1 from PLL3
01
1
N/A
1
0
24.576 24.576
None
24.576Mhz on SE1 and SE2
1
0
1
24.576 98.304
None
24.576Mhz on SE1, 98.304Mhz on SE2
1
0
1
0
98.304 98.304
None
98.304Mhz on SE1 and SE2
1
0
1
27.000 27.000
None
27Mhz on SE1 and SE2
1
0
25.000 25.000
None
25Mhz on SE1 and SE2
11
0
1
N/A
11
1
0
N/A
11
1
N/A
B1b1
B1b4 B1b3 B1b2
Table 2: PLL3 Quick Configuration (only applies in Mode 0, see Table 6)
Comment
PLL 3 disabled
相關(guān)PDF資料
PDF描述
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