參數(shù)資料
型號(hào): 9FG108CFLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48
文件頁(yè)數(shù): 19/21頁(yè)
文件大?。?/td> 263K
代理商: 9FG108CFLFT
IDTTM/ICSTM
Frequency Generator for CPU, FBD, PCIe Gen 1/2 & SATA
ICS9FG108
REV J 02/20/09
ICS9FG108
Frequency Generator for CPU, FBD, PCIe Gen 1/2 & SATA
7
Electrical Characteristics - REF-14.318/25 MHz (Commercial)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
0
300
ppm
1
Clock period
Tperiod
14.318MHz output nominal
69.8270 69.8413 69.8550
ns
1,2
Clock period
Tperiod
25.000MHz output nominal
39.9880 40.0000 40.0120
ns
1,2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
1
Output High Current
IOH
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
-29
-23
mA
1
Output Low Current
IOL
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
29
27
mA
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
1
1.6
2
ns
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
1.6
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter
tjcyc-cyc
VT = 1.5 V
150
350
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or
25.00 MHz
Electrical Characteristics - Phase Jitter (Commercial)
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP.
MAX
UNITS
NOTES
tjphPCIe1
PCIe Gen 1 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54,
Td=10 ns, Ftrk=1.5 MHz )
36/41
86
ps
1,2,3,4
tjphPCIe2Lo
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Lo-band content
(10kHz to 1.5MHz)
0.7/0.8
3
ps rms
1,2,4,5
tjphPCIe2Hi
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Hi-band content
(1.5MHz to Nyquist)
1.8/1.9
3.1
ps rms
1,2,4,5
tjphFBD1_3.2G
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
1.7/1.8
3
ps
(RMS)
1,2,4,5
tjphFBD1_4.8G
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
1.3/1.4
2.5
ps
(RMS)
1,2,4,5
Notes on Phase Jitter:
2 Device driven 14.318MHz and 25MHz crystal
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12
4 First number is with Spread Spectum off, second number is with Spread Spectum off.
5 Only Applies to Rev D and higher devices.
1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.
Jitter, Phase
相關(guān)PDF資料
PDF描述
9FG108CFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9FG108CGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9FG108DFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9FG108DFILF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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