參數(shù)資料
型號: 9FG1200DF-1LFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù): 9/23頁
文件大?。?/td> 188K
代理商: 9FG1200DF-1LFT
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
ICS9FG1200D-1
17
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: 1:1 PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
1:1 PLL M Div5
RW
X
Bit 4
1:1 PLL M Div4
RW
X
Bit 3
1:1 PLL M Div3
RW
X
Bit 2
1:1 PLL M Div2
RW
X
Bit 1
1:1 PLL M Div1
RW
X
Bit 0
1:1 PLL M Div0
RW
X
SMBus Table: 1:1 PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
1:1 PLL N Div7
RW
X
Bit 6
1:1 PLL N Div6
RW
X
Bit 5
1:1 PLL N Div5
RW
X
Bit 4
1:1 PLL N Div4
RW
X
Bit 3
1:1 PLL N Div3
RW
X
Bit 2
1:1 PLL N Div2
RW
X
Bit 1
1:1 PLL N Div1
RW
X
Bit 0
1:1 PLL N Div0
RW
X
SMBusTable: 1:1 PLL Output Divider Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1outDiv 3
RW
X
Bit 2
1outDiv 2
RW
X
Bit 1
1outDiv 1
RW
X
Bit 0
1outDiv 1
RW
X
RESERVED
N Divider Programming
bits
Contact IDT for 9FG1200-
1 M/N programming Table
RESERVED
Contact IDT for 9FG1200-
1 M/N programming Table
-
Byte 18
Byte 17
-
Byte 19
-
Byte 16
M Divider Programming
bits
RESERVED
1:1 Output Divider
Contact IDT for Output
Divider Table
RESERVED
相關(guān)PDF資料
PDF描述
9FG1200DG-1LF 400 MHz, OTHER CLOCK GENERATOR, PDSO56
9FG1200DF-1LF 400 MHz, OTHER CLOCK GENERATOR, PDSO56
9FG1200YG-1LF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
9FG1200YF-1LF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
9FG1201HGLF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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