參數(shù)資料
型號: 9FG1200YF-1LF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.635 MM PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù): 11/23頁
文件大?。?/td> 286K
代理商: 9FG1200YF-1LF-T
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
19
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
Unit
Figure
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
1
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
1
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
1
Rs
33
ohm
1
Rt
49.9
ohm
1
Down Device Differential Routing
Dimension or Value
Unit
Figure
L4 length, Route as coupled microstrip 100 ohm differential trace.
2 min to 16 max
inch
1
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max
inch
1
Differential Routing to PCIe Connector
Dimension or Value
Unit
Figure
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max
inch
2
L4 length, Route as coupled stripline 100 ohm differential trace.
0.225 min to 12.6 max
inch
2
Figure 1 Down device routing.
Rs
Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
REF_CLK Input
L1
L2
L3’
L4
L1’
L2
L3
L4’
Figure 1
Figure 2 PCIe Connector Routing.
Rs
Rt
HSCL Output
Buffer
PCI Ex
Add In Board
REF_CLK Input
L1
L2
L3’
L4
L1’
L2’
L3
L4’
Figure 2
相關(guān)PDF資料
PDF描述
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