參數(shù)資料
型號： 9FG1200YG-1LF-T
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁數(shù)： 18/23頁
文件大小： 286K
代理商： 9FG1200YG-1LF-T
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
4
Pin Description (continued)
PIN # PIN NAME
TypePin Description
29
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
30
SMB_A2_PLLBYP#
IN
SMBus address bit 2. When Low, the part operates as a fanout buffer
with the PLL bypassed. When High, the part operates as a zero-delay
buffer (ZDB) with the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
31
OE6#
IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
32
DIF_6#
OUT
0.7V differential complement clock output
33
DIF_6
OUT
0.7V differential true clock output
34
OE7#
IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
35
DIF_7#
OUT
0.7V differential complement clock output
36
DIF_7
OUT
0.7V differential true clock output
37
GND
PWR
Ground pin.
38
VDD
PWR
Power supply, nominal 3.3V
39
DIF_8#
OUT
0.7V differential complement clock output
40
DIF_8
OUT
0.7V differential true clock output
41
OE8#
IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
42
DIF_9#
OUT
0.7V differential complement clock output
43
DIF_9
OUT
0.7V differential true clock output
44
OE9#
IN
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
45
VTT_PWRGD#/PD
IN
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
46
FS_A_410
IN
3.3V tolerant low threshold input for CPU frequency selection. This
pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
47
DIF_10#
OUT
0.7V differential complement clock output
48
DIF_10
OUT
0.7V differential true clock output
49
GND
PWR
Ground pin.
50
VDD
PWR
Power supply, nominal 3.3V
51
DIF_11#
OUT
0.7V differential complement clock output
52
DIF_11
OUT
0.7V differential true clock output
53
OE10_11#
IN
Active low input for enabling output pairs 10 and 11.
1 = tri-state outputs, 0 = enable outputs
54
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
55
GNDA
PWR
Ground pin for the PLL core.
56
VDDA
PWR
3.3V power for the PLL core.
相關PDF資料
PDF描述
9FG1200YF-1LF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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相關代理商/技術參數(shù)
參數(shù)描述
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9FG1201CGLFT 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標準包裝:1,000
9FG1201HFLF 功能描述:時鐘緩沖器 12 Output PCIe Gearng Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9FG1201HFLFT 功能描述:時鐘緩沖器 12 Output PCIe Gearng Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9FG1201HGLF 功能描述:時鐘緩沖器 12 Output PCIe Gearng Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
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