參數(shù)資料
型號: 9FG830AGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
文件頁數(shù): 6/19頁
文件大?。?/td> 219K
代理商: 9FG830AGLFT
IDT Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
14
SMBus Table: Frequency Select Readback Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
SEL14M_25M#
1
(FS3)
State of pin 27
R
Pin 27
Bit 6
FS2
1
State of pin 6
R
Pin 6
Bit 5
FS1
1
State of pin 44
R
Pin 44
Bit 4
FS0
1
State of pin 45
R
Pin 45
Bit 3
SPREAD
1
State of pin 26
R
Off
On
Pin 26
Bit 2
R
X
Bit 1
R
X
Bit 0
R
X
Notes:
1. These bits reflect the state of the corresponding pins, regardless of whether software
programming is enabled or not.
SMBus Table: Vendor & Revision ID Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
RID3
R
-
X
Bit 6
RID2
R
-
X
Bit 5
RID1
R
-
X
Bit 4
RID0
R
-
X
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBus Table: DEVICE ID
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DEVID7
R
1
Bit 6
DEVID6
R
0
Bit 5
DEVID5
R
0
Bit 4
DEVID4
R
0
Bit 3
DEVID3
R
0
Bit 2
DEVID2
R
0
Bit 1
DEVID1
R
1
Bit 0
DEVID0
R
1
SMBus Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
0
Bit 2
BC2
RW
-
1
Bit 1
BC1
RW
-
1
Bit 0
BC0
RW
-
1
Device ID = 83 hex
Reserved
Byte 3
6
27
45
44
See Frequency
Selection Table.
26
Reserved
Byte 4
-
REVISION ID
-
VENDOR ID
-
Byte 5
-
Byte 6
Writing to this register
will configure how many
bytes will be read back,
default is 07 = 7 bytes.
-
相關PDF資料
PDF描述
9FG830AGILFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9FG830AGILF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9FG830AFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9FG830AFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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