A1 41 00 A Ti m i ng Cha r act e r i s t i cs (continued) (W or s t - C as e M i l " />
參數資料
型號: A1020B-1PG84C
廠商: Microsemi SoC
文件頁數: 41/98頁
文件大小: 0K
描述: IC FPGA 2K GATES 84-CPGA COM
標準包裝: 21
系列: ACT™ 1
LAB/CLB數: 547
輸入/輸出數: 69
門數: 2000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 通孔
工作溫度: 0°C ~ 70°C
封裝/外殼: 84-BCPGA
供應商設備封裝: 84-CPGA(28x28)
46
A1 41 00 A Ti m i ng Cha r act e r i s t i cs (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
ns
tDLS
Data to Pad, Low Slew
17.3
20.3
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
7.7
9.1
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
13.1
15.5
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
11.6
14.0
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.9
12.8
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
14.4
16.0
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
20.2
22.4
ns
dTLHHS
Delta Low to High, High Slew
0.06
0.07
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.11
0.13
ns/pF
dTHLHS
Delta High to Low, High Slew
0.04
0.05
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.05
0.06
ns/pF
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
3.5
4.1
ns
tIOPWH
Minimum Pulse Width High
4.8
5.7
ns
tIOPWL
Minimum Pulse Width Low
4.8
5.7
ns
tIOSAPW
Minimum Asynchronous Pulse Width
3.9
4.4
ns
tIOCKSW
Maximum Skew
0.9
1.0
ns
tIOP
Minimum Period
9.9
11.6
ns
fIOMAX
Maximum Frequency
100
85
MHz
Dedicated (Hard-Wired) Array Clock Network
tHCKH
Input Low to High
(Pad to S-Module Input)
5.5
6.4
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
5.5
6.4
ns
tHPWH
Minimum Pulse Width High
4.8
5.7
ns
tHPWL
Minimum Pulse Width Low
4.8
5.7
ns
tHCKSW
Maximum Skew
0.9
1.0
ns
tHP
Minimum Period
9.9
11.6
ns
fHMAX
Maximum Frequency
100
85
MHz
Notes:
1.
Delays based on 35 pF loading.
2.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
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