A1 28 0XL Ti m i ng Cha r act e r i s t i cs (continued) (W or s " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1020B-2PL84I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 29/98闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 2K GATES 84-PLCC IND
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 16
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 547
杓稿叆/杓稿嚭鏁�(sh霉)锛� 69
闁€鏁�(sh霉)锛� 2000
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 84-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 84-PLCC锛�29.31x29.31锛�
35
Hi R e l F P GA s
A1 28 0XL Ti m i ng Cha r act e r i s t i cs (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data to Pad High
5.3
6.2
ns
tDHL
Data to Pad Low
5.7
6.6
ns
tENZH
Enable Pad Z to High
5.3
6.2
ns
tENZL
Enable Pad Z to Low
5.8
6.8
ns
tENHZ
Enable Pad High to Z
7.5
8.9
ns
tENLZ
Enable Pad Low to Z
7.5
8.9
ns
tGLH
G to Pad High
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
Delta Low to High
0.05
0.06
ns/pF
dTHL
Delta High to Low
0.05
0.09
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
6.6
7.9
ns
tDHL
Data to Pad Low
4.7
5.5
ns
tENZH
Enable Pad Z to High
5.3
6.2
ns
tENZL
Enable Pad Z to Low
5.8
6.8
ns
tENHZ
Enable Pad High to Z
7.5
8.9
ns
tENLZ
Enable Pad Low to Z
7.5
8.9
ns
tGLH
G to Pad High
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
Delta Low to High
0.07
0.09
ns/pF
dTHL
Delta High to Low
0.06
0.09
ns/pF
Notes:
1.
Delays based on 50 pF loading.
2.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
AX250-2FG256I IC FPGA AXCELERATOR 250K 256FBGA
CAT25320YI-GT3 IC EEPROM SER 32KB 10MHZ 8TSSOP
AX250-2FGG256I IC FPGA AXCELERATOR 250K 256FBGA
M1AFS600-2FG256I IC FPGA 4MB FLASH 600K 256-FBGA
24VL024HT/SN IC EEPROM 2KBIT 400KHZ 8SOIC
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A1020B-2PL84M 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs
A1020B-2PLG44C 鍔熻兘鎻忚堪:IC FPGA 2K GATES 44-PLCC COM RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1020B-2PLG44I 鍔熻兘鎻忚堪:IC FPGA 2K GATES 44-PLCC IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ACT™ 1 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛�
A1020B-2PLG68C 鍔熻兘鎻忚堪:IC FPGA 2K GATES 68-PLCC COM RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1020B-2PLG68I 鍔熻兘鎻忚堪:IC FPGA 2K GATES 68-PLCC IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ACT™ 1 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛�