(Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC <" />
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    參數(shù)資料
    型號: A1020B-2PLG68C
    廠商: Microsemi SoC
    文件頁數(shù): 48/98頁
    文件大?。?/td> 0K
    描述: IC FPGA 2K GATES 68-PLCC COM
    標準包裝: 19
    系列: ACT™ 1
    LAB/CLB數(shù): 547
    輸入/輸出數(shù): 57
    門數(shù): 2000
    電源電壓: 4.5 V ~ 5.5 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 68-LCC(J 形引線)
    供應商設備封裝: 68-PLCC(24.23x24.23)
    52
    A3 22 00 DX Ti m i n g Ch ar ac te r i st i c s
    (Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
    ‘–1’ Speed
    ‘Std’ Speed
    Parameter
    Description
    Min.
    Max.
    Min.
    Max.
    Units
    Logic Module Combinatorial Functions
    tPD
    Internal Array Module Delay
    2.8
    3.8
    ns
    tPDD
    Internal Decode Module Delay
    3.4
    4.6
    ns
    Logic Module Predicted Routing Delays1
    tRD1
    FO=1 Routing Delay
    1.6
    2.1
    ns
    tRD2
    FO=2 Routing Delay
    2.3
    3.1
    ns
    tRD3
    FO=3 Routing Delay
    2.9
    3.9
    ns
    tRD4
    FO=4 Routing Delay
    3.5
    4.7
    ns
    tRD5
    FO=8 Routing Delay
    6.2
    8.2
    ns
    tRDD
    Decode-to-Output Routing Delay
    0.8
    1.1
    ns
    Logic Module Sequential Timing Characteristics
    tCO
    Flip-Flop Clock-to-Output
    3.2
    4.2
    ns
    tGO
    Latch Gate-to-Output
    2.8
    3.8
    ns
    tSU
    Flip-Flop (Latch) Setup Time
    0.5
    0.6
    ns
    tH
    Flip-Flop (Latch) Hold Time
    0.0
    ns
    tRO
    Flip-Flop (Latch) Reset to Output
    3.2
    4.2
    ns
    tSUENA
    Flip-Flop (Latch) Enable Setup
    0.9
    1.2
    ns
    tHENA
    Flip-Flop (Latch) Enable Hold
    0.0
    ns
    tWCLKA
    Flip-Flop (Latch) Clock Active Pulse Width
    4.3
    5.8
    ns
    tWASYN
    Flip-Flop (Latch) Asynchronous Pulse Width
    5.7
    7.6
    ns
    Note:
    1.
    Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
    performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
    based on actual routing delay measurements performed on the device prior to shipment.
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