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參數(shù)資料
| 型號： | A1186LUA-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 509K |
| 描述： | IC SWITCH HALL EFFECT UNI 3-SIP |
| 產(chǎn)品培訓模塊： | Current Sensor |
| 標準包裝： | 500 |
| 傳感范圍： | 10G ~ 60G 跳閘 - 可編程，固定釋放 |
| 類型： | 單極開關 |
| 電源電壓： | 3.5 V ~ 24 V |
| 電流 - 電源： | 6.9mA |
| 輸出類型： | 數(shù)字，開路集電極 |
| 特點： | 可編程 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 3-SIP |
| 供應商設備封裝： | 3-SIP |
| 包裝： | 散裝 |
Ultrasensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1185 and
A1186
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
V
PH
V+
t
V
PM
V
PL
0
Encode 00100
2
(4
10
)
Enable
Address
Address
Blow
Blow
Enable
Encode 00001
2
(1
10
)
Figure 6. Pulse sequence to permanently encode calibration value 5 (101 binary, or
bitfield address 3 and bitfield address 1).
V
PH
V+
t
V
PM
V
PL
0
Try 5
10
Enable
Address
Clear
Optional
Monitoring
The pulse sequences consist of the following groups of pulses:
1. An enable sequence.
2. A bitfield address sequence.
3. When permanently setting the bitfield, a long V
PH
fuse-blow-
ing pulse. (Note: Blown bit fuses cannot be reset.)
4. When permanently setting the bitfield, the level of V
CC
must
be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally set-
ting bitfields, V
CC
must be maintained at V
PL
between pulse
sequences, in order to maintain the prior bitfield settings while
preparing to set additional bitfields.
Bitfields that are not set are evaluated as zeros. The bitfield-level
fuses for 0 value bitfields are never blown. This prevents inad-
vertently setting the bitfield to 1. Instead, blowing the device-
level fuse protects the 0 bitfields from being accidentally set in
the future.
When provisionally trying the calibration value, one pulse
sequence is used, using decimal values. The sequence for setting
the value 5
10
is shown in figure 5.
When permanently setting values, the bitfields must be set indi-
vidually, and 5
10
must be programmed as binary 101. Bit 3 is
set to 1 (000100
2
, which is 4
10
), then bit 1 is set to 1 (000001
2
,
which is 1
10
). Bit 2 is ignored, and so remains 0.Two pulse
sequences for permanently setting the calibration value 5 are
shown in figure 6. The final V
PH
pulse is maintained for a longer
period, enough to blow the corresponding bitfield-level fuse.
Figure 5. Pulse sequence to provisionally try calibration value 5.
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