參數(shù)資料
型號: A1225A-PQ100I
廠商: Microsemi SoC
文件頁數(shù): 3/54頁
文件大?。?/td> 0K
描述: IC FPGA 2500 GATES 100-PQFP IND
產(chǎn)品變化通告: A1225A Family Discontinuation 18/Apr/2012
標準包裝: 66
系列: ACT™ 2
LAB/CLB數(shù): 451
輸入/輸出數(shù): 83
門數(shù): 2500
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-BQFP
供應商設備封裝: 100-PQFP(14x20)
ACT 2 Family FPGAs
R e visio n 8
2 -5
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. EQ 4 shows a piece-wise linear summation over all components.
Power =VCC2 * [(m * CEQM * fm)modules + (n * CEQI * fn) inputs
+ (p * (CEQO+ CL) * fp)outputs
+ 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
+ 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2
EQ 4
Where:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1 = Number of clock loads on the first routed array clock
q2 = Number of clock loads on the second routed array clock
r1 = Fixed capacitance due to first routed array clock
r2 = Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL = Output lead capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
Table 2-7 Fixed Capacitance Values for Microsemi FPGAs
Device Type
r1, routed_Clk1
r2, routed_Clk2
A1225A
106
106.0
A1240A
134
134.2
A1280A
168
167.8
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