Table 2-18 A1280A Worst-Case Commercial Conditions, VCC = " />
  • <li id="qbkmr"><tr id="qbkmr"><xmp id="qbkmr"></xmp></tr></li>
    參數(shù)資料
    型號： A1240A-1PQ144C
    廠商： Microsemi SoC
    文件頁數(shù)： 17/54頁
    文件大?。?/td> 0K
    描述： IC FPGA 4K GATES 144-PQFP COM
    標準包裝： 24
    系列： ACT™ 2
    LAB/CLB數(shù)： 684
    輸入/輸出數(shù)： 104
    門數(shù)： 4000
    電源電壓： 4.5 V ~ 5.5 V
    安裝類型： 表面貼裝
    工作溫度： 0°C ~ 70°C
    封裝/外殼： 144-BQFP
    供應商設(shè)備封裝： 144-PQFP（28x28）
    Detailed Specifications
    2- 18
    R e visio n 8
    A1280A Timing Characteristics
    Table 2-18 A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
    Logic Module Propagation Delays1
    –2 Speed3
    –1 Speed
    Std. Speed
    Units
    Parameter/Description
    Min.
    Max.
    Min.
    Max.
    Min.
    Max.
    tPD1
    Single Module
    3.8
    4.3
    5.0
    ns
    tCO
    Sequential Clock to Q
    3.8
    4.3
    5.0
    ns
    tGO
    Latch G to Q
    3.8
    4.3
    5.0
    ns
    tRS
    Flip-Flop (Latch) Reset to Q
    3.8
    4.3
    5.0
    ns
    Predicted Routing Delays2
    tRD1
    FO = 1 Routing Delay
    1.7
    2.0
    2.3
    ns
    tRD2
    FO = 2 Routing Delay
    2.5
    2.8
    3.3
    ns
    tRD3
    FO = 3 Routing Delay
    3.0
    3.4
    4.0
    ns
    tRD4
    FO = 4 Routing Delay
    3.7
    4.2
    4.9
    ns
    tRD8
    FO = 8 Routing Delay
    6.7
    7.5
    8.8
    ns
    Sequential Timing Characteristics3,4
    tSUD
    Flip-Flop (Latch) Data Input Setup
    0.4
    0.5
    ns
    tHD
    Flip-Flop (Latch) Data Input Hold
    0.0
    ns
    tSUENA
    Flip-Flop (Latch) Enable Setup
    0.8
    0.9
    1.0
    ns
    tHENA
    Flip-Flop (Latch) Enable Hold
    0.0
    ns
    tWCLKA
    Flip-Flop (Latch) Clock Active Pulse Width
    5.5
    6.0
    7.0
    ns
    tWASYN
    Flip-Flop (Latch) Clock Asynchronous Pulse Width
    5.5
    6.0
    7.0
    ns
    tA
    Flip-Flop Clock Input Period
    11.7
    13.3
    18.0
    ns
    tINH
    Input Buffer Latch Hold
    0.0
    ns
    tINSU
    Input Buffer Latch Setup
    0.4
    0.5
    ns
    tOUTH
    Output Buffer Latch Hold
    0.0
    ns
    tOUTSU
    Output Buffer Latch Setup
    0.4
    0.5
    ns
    fMAX
    Flip-Flop (Latch) Clock Frequency
    85.0
    75.0
    50.0
    MHz
    Notes:
    1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD —whichever is appropriate.
    2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
    estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
    performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
    shipment.
    3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
    can be obtained from the DirectTime Analyzer utility.
    4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External
    setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
    PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
    相關(guān)PDF資料
    PDF描述
    A3PE3000-1PQ208I IC FPGA 1KB FLASH 3M 208-PQFP
    M1A3PE3000-1PQ208I IC FPGA 1KB FLASH 3M 208-PQFP
    A3PE3000-1PQG208I IC FPGA 1KB FLASH 3M 208-PQFP
    IDT70V631S10BC IC SRAM 4MBIT 10NS 256BGA
    M1A3PE3000-1PQG208I IC FPGA 1KB FLASH 3M 208-PQFP
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    A1240A-1PQ144I 功能描述:IC FPGA 4K GATES 144-PQFP IND RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 2 標準包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應商設(shè)備封裝:352-CQFP（75x75）
    A1240A-1PQ144M 制造商:Microsemi Corporation 功能描述:FPGA ACT 2 4K GATES 684 CELLS 110MHZ 1.0UM 5V 144PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 4K GATES 144-PQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 104 I/O 144PQFP
    A1240A-1PQ160B 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:ACT 2 Family FPGAs
    A1240A-1PQ160C 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:ACT 2 Family FPGAs
    A1240A-1PQ160I 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:ACT 2 Family FPGAs
    發(fā)布緊急采購，3分鐘左右您將得到回復。

    采購需求

    (若只采購一條型號，填寫一行即可)

    發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

    發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

    *型號 *數(shù)量 廠商 批號 封裝
    添加更多采購

    我的聯(lián)系方式

    *
    *
    *