Table 2-19 A1280A Worst-Case Commercial Conditions" />
參數(shù)資料
型號(hào)： A1240A-1PQG144C
廠商： Microsemi SoC
文件頁(yè)數(shù)： 18/54頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 4K GATES 144-PQFP COM
標(biāo)準(zhǔn)包裝： 24
系列： ACT™ 2
LAB/CLB數(shù)： 684
輸入/輸出數(shù)： 104
門(mén)數(shù)： 4000
電源電壓： 4.5 V ~ 5.5 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 144-BQFP
供應(yīng)商設(shè)備封裝： 144-PQFP（28x28）
ACT 2 Family FPGAs
R e visio n 8
2 - 19
A1280A Timing Characteristics (continued)
Table 2-19 A1280A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min.
Max.
Min.
Max.
Min.
Max.
tINYH
Pad to Y High
2.9
3.3
3.8
ns
tINYL
Pad to Y Low
2.7
3.0
3.5
ns
tINGH
G to Y High
5.0
5.7
6.6
ns
tINGL
G to Y Low
4.8
5.4
6.3
ns
Input Module Predicted Input Routing Delays*
tIRD1
FO = 1 Routing Delay
4.6
5.1
6.0
ns
tIRD2
FO = 2 Routing Delay
5.2
5.9
6.9
ns
tIRD3
FO = 3 Routing Delay
5.6
6.3
7.4
ns
tIRD4
FO = 4 Routing Delay
6.5
7.3
8.6
ns
tIRD8
FO = 8 Routing Delay
9.4
10.5
12.4
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
10.2
11.0
12.8
ns
FO = 256
13.1
14.6
17.2
tCKL
Input High to Low
FO = 32
10.2
11.0
12.8
ns
FO = 256
13.3
14.9
17.5
tPWH
Minimum Pulse Width High
FO = 32
5.0
5.5
6.6
ns
FO = 256
5.8
6.4
7.6
tPWL
Minimum Pulse Width Low
FO = 32
5.0
5.5
6.6
ns
FO = 256
5.8
6.4
7.6
tCKSW
Maximum Skew
FO = 32
0.5
ns
FO = 256
2.5
tSUEXT
Input Latch External Setup
FO = 32
0.0
ns
FO = 256
0.0
tHEXT
Input Latch External Hold
FO = 32
7.0
ns
FO = 256
11.2
tP
Minimum Period
FO = 32
9.6
11.2
13.3
ns
FO = 256
10.6
12.6
15.3
fMAX
Maximum Frequency
FO = 32
105.0
90.0
75.0
ns
FO = 256
95.0
80.0
65.0
Note:
*These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-
route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
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參數(shù)描述
A1240A-1PQG144I 功能描述:IC FPGA 4K GATES 144-PQFP IND RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ACT™ 2 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門(mén)數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類(lèi)型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A1240A-1PQG144M 制造商:Microsemi Corporation 功能描述:FPGA ACT 2 4K GATES 684 CELLS 110MHZ 1.0UM 5V 144PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 4K GATES 144-PQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 104 I/O 144PQFP
A1240A-1PQG160B 制造商:MICROSEMI 制造商全稱(chēng):Microsemi Corporation 功能描述:ACT 2 Family FPGAs
A1240A-1PQG160C 制造商:MICROSEMI 制造商全稱(chēng):Microsemi Corporation 功能描述:ACT 2 Family FPGAs
A1240A-1PQG160I 制造商:MICROSEMI 制造商全稱(chēng):Microsemi Corporation 功能描述:ACT 2 Family FPGAs
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