Table 2-17 A1240A Worst-Case Commercial Conditions" />
參數(shù)資料
型號: A1280A-1PG176C
廠商: Microsemi SoC
文件頁數(shù): 16/54頁
文件大小: 0K
描述: IC FPGA 8K GATES 176-CPGA COM
標準包裝: 21
系列: ACT™ 2
LAB/CLB數(shù): 1232
輸入/輸出數(shù): 140
門數(shù): 8000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 176-BCPGA
供應商設備封裝: 176-CPGA(39.88x39.88)
ACT 2 Family FPGAs
R e visio n 8
2 - 17
A1240A Timing Characteristics (continued)
Table 2-17 A1240A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
TTL Output Module Timing1
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min.
Max.
Min.
Max.
Min.
Max.
tDLH
Data to Pad High
8.0
9.0
10.6
ns
tDHL
Data to Pad Low
10.1
11.4
13.4
ns
tENZH
Enable Pad Z to High
8.9
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.7
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.2
12.7
14.9
ns
dTLH
Delta Low to High
0.07
0.08
0.09
ns/pF
dTHL
Delta High to Low
0.12
0.13
0.16
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.2
11.5
13.5
ns
tDHL
Data to Pad Low
8.4
9.6
11.2
ns
tENZH
Enable Pad Z to High
8.9
10.0
11.8
ns
tENZL
Enable Pad Z to Low
11.7
13.2
15.5
ns
tENHZ
Enable Pad High to Z
7.1
8.0
9.4
ns
tENLZ
Enable Pad Low to Z
8.4
9.5
11.1
ns
tGLH
G to Pad High
9.0
10.2
11.9
ns
tGHL
G to Pad Low
11.2
12.7
14.9
ns
dTLH
Delta Low to High
0.12
0.13
0.16
ns/pF
dTHL
Delta High to Low
0.09
0.10
0.12
ns/pF
Notes:
1. Delays based on 50 pF loading.
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