參數(shù)資料
型號(hào): A1280A-1PL84C
廠商: Microsemi SoC
文件頁(yè)數(shù): 9/54頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 8K GATES 84-PLCC COM
標(biāo)準(zhǔn)包裝: 16
系列: ACT™ 2
LAB/CLB數(shù): 1232
輸入/輸出數(shù): 72
門(mén)數(shù): 8000
電源電壓: 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 84-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 84-PLCC(29.31x29.31)
ACT 2 Family FPGAs
R e visio n 8
2 - 11
Timing Derating Factor (Temperature and Voltage)
Table 2-9 Timing Derating Factor (Temperature and Voltage)
(Commercial Minimum/Maximum Specification) x
Industrial
Military
Min.
Max.
Min.
Max.
0.69
1.11
0.67
1.23
Table 2-10 Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C)
and Voltage (5.0 V)
(Commercial Maximum Specification) x
0.85
Table 2-11 Temperature and Voltage Derating Factors
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
–55
–40
0
257085
125
4.50
0.75
0.79
0.86
0.92
1.06
1.11
1.23
4.75
0.71
0.75
0.82
0.87
1.00
1.05
1.13
5.00
0.69
0.72
0.80
0.85
0.97
1.02
1.13
5.25
0.68
0.69
0.77
0.82
0.95
0.98
1.09
5.50
0.67
0.69
0.76
0.81
0.93
0.97
1.08
Note:
This derating factor applies to all routing and propagation delays.
Figure 2-9
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
4.504.755.005.255.50
r
ot
c
a
F
g
nit
ar
e
D
Voltage (V)
125C
85C
70C
25C
0C
–40C
–55C
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