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參數(shù)資料
| 型號： | A14100A-CQ256C |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 4/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 10K GATES 256-CQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ACT™ 3 |
| LAB/CLB數(shù)： | 1377 |
| 輸入/輸出數(shù)： | 228 |
| 門數(shù)： | 10000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 256-BFCQFP，帶拉桿 |
| 供應(yīng)商設(shè)備封裝： | 256-CQFP（75x75） |
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Detailed Specifications
2- 4
R e v ision 3
The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into
the array. This allows the output register to be used in high-speed state machine applications. Side I/O
modules have a dedicated output segment for Y extending into the routing channels above and below
(similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained
in detail in the routing section).
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four
signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only
during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN
(global input enable), and SLEW (individual slew selection). See Figure 2-5.
Special I/Os
The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during
programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent
special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change
once the device has been programmed. The permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input
buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is
determined by the I/O macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks
and two general purpose routed networks. The high-performance networks function up to 200 MHz,
while the general purpose routed networks function up to 150 MHz.
Figure 2-5
Function Diagram for I/O Pad Driver
PAD
OE
SLEW
DATAOUT
DATAIN
IEN
INEN
OUTEN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A14100A-CQ256M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 10K Gates 1377 Cells 100MHz 0.8um Technology 5V 256-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 100MHZ 0.8UM 5V 256CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 256-CQFP MIL |
| A14100A-PG257B | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 100MHZ 0.8UM 5V 257CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 257-CPGA MIL |
| A14100A-PG257C | 功能描述:IC FPGA 10K GATES 257-CPGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A14100A-PG257M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 10K Gates 1377 Cells 100MHz 0.8um Technology 5V 257-Pin CPGA 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 100MHZ 0.8UM 5V 257CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 257-CPGA MIL |
| A14100A-RQ208C | 功能描述:IC FPGA 10K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
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